In a synchronous communications network, digital payload data is carried on a particular clock frequency within a synchronous message format. This payload data may include both asynchronous digital data and synchronous digital data originating at a different data rate in a foreign digital network. The Synchronous Optical Network (SONET) and its European counterpart the Synchronous Digital Hierarchy (SDH) provide a standard format of transporting digital signals having various data rates, such as a DS-0, DS-1, DS-1C, DS-2, or a DS-3 signal and their European counterparts within a Synchronous Payload Envelope (SPE), or a container that is a part of a SONET/SDH STS-N/STM-N message frame. In addition to the digital data that is mapped and framed within the SPE or container, the STS-N/STM-N message frame also includes overhead data that provides for coordination between various network elements.
One of the benefits of SONET is that it can carry large payloads (above 50 Mb/s). However, the existing slower speed digital hierarchy can be accommodated as well, thus protecting investments in current equipment. To achieve this capacity, the STS Synchronous Payload Envelope (SPE) can be sub-divided into smaller components or structures, known as Virtual Tributaries (VT) for the purpose of transporting and switching payloads smaller than the STS-1 rate. All services below the DS3 and E-3 rates are transported in the VT structure.
If the digital data that is mapped and framed in the STS-N/STM-N message was originally carried by a clock signal having a different frequency than the SONET/SDH line rate clock, certain adjustments to the framed digital data must be made. For example, if a DS-3 data signal, which is carried by a 44.736 MHz DS-3 clock signal is to be carried in a SONET/SDH fiber-optic network, the DS-3 signal is mapped into the higher rate SPE of an STS-1 message, and extra bytes must be added to the DS-3 signal prior to transmission through the SONET/SDH network. These extra bits are commonly referred to as stuff bits or gap bits and are merely place markers and in general carry no valid data. These gap bits are required because the DS-3 signal is slower than the SONET/SDH clock frequency so that there are not enough DS-3 bits at the higher frequency to form a complete SONET frame. More detail may be found in the Bellcore specification “SONET Transport Systems: Common Generic Criteria”, GR-253-CORE, Issue 3, September 2000, the Bellcore specification “Transport Systems Generic Requirements (TSGR): Common Requirements”, GR-499-CORE, Issue 2, December 1998, and the ITU-T Recommendation G.783, “Characteristic Synchronous Digital Hierarchy (SDH) Equipment Functional Blocks”, January 1994.
When the STS-1 message is received at a network exit node, the overhead bytes are removed from the SONET STS-1 message and replaced by gaps in the data stream. The payload data that remains is de-framed and de-mapped into a data stream carried by a higher clock frequency than the nominal original clock frequency of the payload data. Thus the stuff data that was inserted when the data was mapped into the SPE remains when the data stream is recovered from the SPE and is also replaced by gaps in the data stream. Thus, the recovered payload data contains gaps in the data stream remaining after the overhead bytes and stuff data bits have been removed. If, for example, DS-3 data has been transported via a SONET/SDH network, the DS-3 data must be converted from the SONET clock signal to the lower frequency DS-3 clock signal and the gap data bits must be removed prior to the DS-3 signal being B3ZS-encoded for electrical re-transmission.
To transfer data from one clock domain to another, for example from the DS-3 embedded within the SONET signal rate to the proper DS-3 signal rate, a desynchronizer is used to provide a buffering mechanism between the clock domains. A desynchronizer typically includes an elastic store first-in-first-out memory buffer that receives gapped data recovered from a synchronized data payload as an input at one clock frequency and stores the data in appropriate storage locations. Data is read from the elastic store buffer at a different clock frequency and is provided as output data at that frequency. This output data does not contain the gap data bits that were added when the slower signal was mapped into the faster SONET/SDH STS-1 message.
Once the data has been de-mapped and de-framed from the SPE a phase locked loop (PLL) is typically used to recover the clock information and to adjust the read signal associated with the data stored in the elastic store for transmission downstream as a data signal carried by a smooth clock signal.
As is known, the PLL used to recover the smooth clock signal and smooth data signal is able to smooth out some phase jumps caused by pointer adjustments or asynchronous stuff bits. A PLL is most effective at filtering out high frequency jitter components, i.e., those with a frequency greater than 10 Hz., but is less effective at filtering out the low frequency wander components. Since, typically the wander components are much less than 10 Hz. these wander components are well within the bandwidth of the PLL and are passed without being attenuated. To construct a PLL with a small enough bandwidth to filter the wander components of the phase jumps, large time constants in the PLL control loops would require large component values for the resistors and capacitors used in the PLL. In addition, the large time constants required would result in a PLL that is slow to lock onto the reference signal and would cause long delays in recovering lock after a transient event.
During the transmission of a SONET/SDH message an error may occur resulting in a loss of data. This loss of data may be caused by a loss of the data signal, a loss of the clock signal, a loss of frame, or another error condition may occur. These errors may occur to one or more, or all, of the transported digital signals that have been multiplexed into the SONET/SDH message. In some of these error conditions, an Alarm Indicator Signal (AIS) is generated and certain predetermined bits in the overhead bytes are set. In addition, a predetermined characteristic data signal is provided, by the receiver, in the SONET message payload in lieu of the error data generated by the various pieces of equipment in the absence of a legitimate signal. If the loss of signal were to the entire SONET/SDH message, caused for example by a severed optical fiber, then the predetermined characteristic data signal would be used in lieu of the entire message payload. Typically the characteristic error data signal is a sequence composed entirely of ones, i.e., “1, 1, 1, 1, 1 . . . .”
The predetermined characteristic data signal is provided at an error condition data rate that is within the SONET/SDH specification. However, it is unlikely that the error condition data rate is equivalent to the payload data rate prior to the loss of signal condition occurring. As discussed above, when a PLL that has previously phase locked to an input signal receives the input signal at a new data rate, the PLL must reestablish phase lock at the new input data rate before the output data will be valid. Accordingly, because the characteristic error data signal is at a different data rate than the payload data, the PLL may lose phase lock and have to reacquire phase lock before the output data will be valid. Similarly, when the payload data is restored, the PLL may once again lose phase lock on the characteristic error data rate when the payload data is restored. The time it takes the PLL to reacquire phase lock will result in erroneous data being sent, and a loss of data after restoration of the payload data.
Thus, it would be advantageous to provide a desynchronizer and PLL that provides for less data loss and a quicker capture of data after a loss of signal occurs and upon restoration of the payload data.